1. Field of the Invention
The present invention relates to a semiconductor apparatus, and particularly to a semiconductor apparatus having a double-sided substrate via-hole for an electric connection formed by trenching from both sides of the semiconductor substrate.
2. Description of Related Art
For a semiconductor apparatus especially a semiconductor chip of an analog integrated circuit processing high-frequency transistors and signals, a substrate via-hole is generally used as a ground line instead of wire bonding. The substrate via-hole is a ground line of a semiconductor device formed on the surface of the substrate. The substrate via-hole is formed by providing a through-hole to a semiconductor substrate and a line given with metal plating. For the wire bonding, a flexion of the wire is an inductive component and a diameter of the wire is a resistance component. Thus a ground potential on the semiconductor chip becomes unstable and a high-frequency performance is hard to obtain. Then, by connecting the ground plane of the backside with a semiconductor device formed to the surface using a thicker and shorter line through the substrate via-hole, the inductor and resistance component are suppressed and the semiconductor chip is connected to ground. This improves the high-frequency performance of the semiconductor apparatus.
The substrate via-hole is made by forming a trench in a semiconductor substrate by an etching and forming metal plating in the trench. The method to provide the trench is broadly divided into 3 methods. The first method is to form a trench on the surface where a semiconductor device is provided. A substrate via-hole formed by the first method is referred to as a surface substrate via-hole. The second method is to form a trench on the backside of the semiconductor substrate. A substrate via-hole formed by the second method is referred to as a backside substrate via-hole. The third method is to form a trench from both sides of the semiconductor substrate. A substrate via-hole formed by the third method is referred to as a double-sided substrate via-hole.
The oldest among these via-holes is the backside substrate via-hole. An etching for a semiconductor substrate is initially a wet type using a solution. A wet etching is performed by an undercut with isotropic etching from a photoresist film mask. The cross-sectional shape of the trench is trapezoid. Thus an aperture area of the surface side is narrower than the opening of the backside. In the backside substrate via-hole, a photoresist film as an etching mask is provided on the backside of the substrate. Hence, the backside substrate via-hole requires a special backside photolithography apparatus to align the etching mask for the photoresist film formed to the backside side according to a marking on the surface side.
After that, a high-speed dry etching technique using high-density plasma has been developed that enables to trench a semiconductor substrate to a vertical shape. The surface substrate via-hole can be formed from the surface side. The surface substrate via-hole becomes to be used. To form a surface substrate via-hole, the special backside photolithography apparatus is not necessary. The via-hole is formed using a common stepper photolithography apparatus. That is, the via-hole is formed based on a pattern of a photoresist film mask formed to the surface. However, if a ratio (selectivity) between the thickness of the photoresist etched by a dry etching and thickness of the area in the semiconductor chip to be etched is low, a photoresist film is needed to be thicker than the thickness of the semiconductor substrate. In such case, there has been a problem that the thickness of the photoresist film causes to deteriorate resolution of the opening pattern and it is difficult to provide a fine opening.
A combination of the two via-holes is the double-sided substrate via-hole. For the surface side, a photoresist film with a thickness to obtain fine resolution is used. A substrate is etched by a dry etching to the halfway of the substrate, and metal plating is provided. Furthermore, a trench is provided from the backside with relaxed accuracy. Then a ground line formed in the trench from backside is connected with a line formed in the trench from the surface side. That is, there is a problem in the double-sided substrate via-hole that the number of processes and processing period increase as it requires processes from surface and backside. However the double-sided substrate via-hole enables to trench from the surface side with high accuracy, thus it is able to increase the density of the semiconductor chip.
In a wet etching of a semiconductor substrate, a mixed solution of hydrogen peroxide solution and acid or alkali is used. In this method, firstly hydrogen peroxide solution oxidizes semiconductor crystal. The oxide is dissolved by acid or alkali. For the acid, hydrofluoric acid is used when the semiconductor is Si. On the other hand, when the semiconductor is a compound such as GaAs or InP, sulfuric acid or phosphoric acid or the like is used. However when the temperature rises due to reaction heat of an etching, there is a problem that the adherence of the photoresist film is reduced and the undercut proceeds. Therefore, it is necessary to dilute the acid by water to suppress the etching rate.
In the meantime, in a dry etching of a semiconductor substrate, chlorine (Cl) or bromine (Br) gas is used. In etchings initially, a parallel plate type RIE (Reactive Ion Etching) has been used. After that, in order to increase the etching rate, a high-density plasma type dry etching apparatus has been developed. The high-density plasma type apparatus is broadly categorized as ECR (Electron Cyclotron Resonance) that uses electron cyclotron resonance microwave or ICP (Inductively Coupled Plasma) which is an inductively coupled discharge system. Furthermore, by a method to forcibly cooling a substrate mount using He gas, a high-speed and vertical dry etching was made possible.
However by a chlorine gas etching, semiconductor such as Si, GaAs and InP can be etched at high-speed but there is also a disadvantage that Al, Au and Cu or the like as a line metal is etched. This means that when providing these line metals to the trench of the surface side using a double-sided substrate via-hole and performing a chlorine dry etching from the backside, the line metals provided to the surface side in advance are also etched.
As a related art 1, Japanese Unexamined Patent Application Publication No. 60-134483 discloses a FET (Field Effect Transistor) having a double-sided substrate via-hole. FIGS. 19A and 19B are a top view and cross-sectional diagram showing the structure of the field-effect transistor having a double-sided substrate via-hole. FIG. 19A is a top view of the field-effect transistor and FIG. 19B is a cross-sectional diagram of the field-effect transistor. As shown in FIG. 19B, for the field-effect transistor according to the related art 1, the backside of the lower part of the active layer region 102 for FET that is provided to the surface of the GaAs substrate 101 is trenched to be trapezoid shape (cross-section 110). The trench is formed from one end of the GaAs substrate 101 to reach another end to be strip shape. The portion the trench formed is thinner than the other portion the trench unformed. A ground electrode 109 is provided to the entire backside surface. In an assembling process, when the GaAs substrate 101 is mounted to a metal base, a brazing filler material gets into the trench on the backside and the trench is filled. By this, the field-effect transistor according to the related art 1 reduces the substrate thickness in the heating FET active layer region to reduce the thermal resistance of the region. A source electrode 107 is pulled out in horizontal direction to provide a pad portion. There is a substrate via-hole 108 under the pad portion. The substrate via-hole 108 is connected with the ground electrode 109 in the thinner area the trench formed of the backside of the substrate.
On the other hand, a gate electrode 103 and a drain electrode 104 are taken out over the semi-insulating GaAs substrate 101, which is not trenched and still thick. A gate electrode 103 and a drain electrode 104 is to be the matching circuit 105. Furthermore, a bonding pad 106 is provided to the gate electrode 103 and drain electrode 104. As the substrate of the matching circuit 105 is thick, there is only a small loss. For the matching circuit 105, a line is formed to be tapered (tapered portion 112) corresponding to the slope of a cutting tapered portion 111. This keeps an impedance of the matching circuit 105 to be constant, thereby not losing consistency.
As a related art 2, a manufacturing method of a semiconductor apparatus according to a related art is disclosed Japanese Unexamined Patent Application Publication No. 3-99470. FIGS. 20A to 20D are cross-sectional diagrams illustrating processes to manufacture a double-sided substrate via-hole unit according to the related art 2. In FIGS. 20A to 20D, the semiconductor apparatus in related art includes a GaAs substrate 121, first via-hole 122, second via-hole 123, first via-hole inner metal layer 124, foundation electroless nickel plating layer 125, photoresist layer 126, electroless nickel plating layer 127, electrolytic Au plating layer 128 and projection cutting portion 181.
As shown in FIG. 20A, the first via-hole 122 of approx 30 μm is formed by RIE method or the like from a first surface of the GaAs substrate 121. Inside the via-hole 122, the metal layer 124 is formed by electrolytic gold (Au) plating. After that, the GaAs substrate 121 is processed to have 100 μm thickness by wrapping and polishing etc. The second via-hole 123 is formed by a chemical etching or the like from a second surface side which is opposite side of the first surface of the GaAs substrate 121. At this time, the second via-hole 123 is formed so that the bottom of the metal layer 124 inside the first via-hole 122 is exposed.
Then proceed to the process shown in FIG. 20B. In this process, a palladium (Pd) activation is performed to entire second surface of the GaAs substrate 121 including the inner surface of the second via-hole 123. An electroless nickel (Ni) is plated to form the foundation electroless nickel plating layer 125. By photolithography, the entire second surface of the GaAs substrate 121 excluding the opening of the second via-hole 123 is masked by the photoresist layer 126 or the like. Without Pd activation, a process is performed with electroless Ni plating solution. Then a chemical reduction is performed with the foundation electroless nickel plating layer exposed inside the second via-hole 123 as a catalyst. By performing the above process, the electroless nickel plating layer 127 is filled (see FIG. 20C). The photoresist layer 126 is removed. To the entire second surface of the substrate 121, the electrolytic Au plating layer 128 is formed. After that, a projection part 181 generated by undulation of the filled layer 127 of the second via-hole 123 is polished and chipped off (see FIG. 20D).
The semiconductor device according to the related art 2 forms the trench of the via-hole by RIE method for the surface side and chemical etching for the backside. The via-hole line is electrolytic gold (Au) plating for the surface side and electroless Ni plating for the backside.
As a related art 3, a method of manufacturing a semiconductor apparatus in related art is disclosed Japanese Unexamined Patent Application Publication No. 2004-128352. FIGS. 21A to 21E are cross-sectional diagrams of the semiconductor apparatus in each process to manufacture a double-sided substrate via-hole unit according to the related art 3. As shown in FIG. 21E, the completed semiconductor apparatus includes a semiconductor substrate 202 formed of GaAs or the like, ohmic electrode 204 formed to a principal surface side of the semiconductor substrate 202, insulating film 206, via-hole foundation electrode with barrier metal 210, via-hole electrode 212 and a backside via-hole electrode 214 formed to the backside of the semiconductor substrate 202. Hereinafter, a manufacturing process of the semiconductor apparatus is described with reference to cross-sectional diagrams for each process.
A first process shown in FIG. 21A is described hereinafter. In the first process, the ohmic electrode 204 is formed over the semiconductor substrate 202 using liftoff method. The insulating film 206 is formed over the ohmic electrode 204 using CVD method. Next, an opening of the contact hole 220 is formed to the insulating film 206 to expose the surface of the ohmic electrode 204.
A second process shown in FIG. 21B is described hereinafter. In the second process, a resist 208 is formed in the area over the ohmic electrode 204 and also inside the contact hole 220. An opening pattern is to be formed to the resist 208. With the resist 208 as a mask, a dry etching such as ion trimming is performed. This exposes the surface of the semiconductor substrate 202. Furthermore, with the resist 208 as a mask, the semiconductor substrate 202 is dry etched to reach a predetermined depth by RIE. This forms a via-hole 226. After that, the resist 208 used as a mask is removed.
A third process shown in FIG. 21C is described hereinafter. In the third process, firstly the resist 208 is reconstituted. The resist 208 is formed so that a part of the via-hole 226 and ohmic electrode 204 are exposed and the insulating film 206 is covered. The barrier metal film 210 such as WSi is deposited to the entire surface of the semiconductor chip. The barrier metal film 210 covers inner wall of the via-hole 226, exposed ohmic electrode 204 and resist 208. Over the barrier metal film 210, a resist (not shown) having an opening pattern wider than an opening pattern of the resist 208 is formed. With the resist as a mask, the via-hole electrode 212 is formed by electrolytic plating method.
A fourth process shown in FIG. 21D is described hereinafter. In the fourth process, firstly the resist formed over the barrier metal film 210 is removed. With the via-hole electrode 212 as a mask, the exposed barrier metal film 210 is removed. The exposed resist 208 is removed. From the backside of the semiconductor substrate 202, a backside via-hole 232 is formed so that the barrier metal film 210 of the bottom of the via-hole 226 is exposed.
A fifth process shown in FIG. 21E is described hereinafter. In the fifth process, to the backside of the semiconductor substrate 202 including the inside of the backside via-hole 232, the backside via-hole electrode 214 is formed by electrolytic plating method. The semiconductor apparatus of the related art 3 is obtained from the above processes.
In the semiconductor apparatus according to a related art 3, the barrier metal film 210 as a foundation of the via-hole electrode 212 on the surface side is WSi and aims to prevent interdiffusion between the via-hole electrode 212 and ohmic electrode 204. Such semiconductor apparatus is disclosed in Japanese Unexamined Patent Application Publication No. 8-46042, which is a related art 4.
As described above, to form a double-sided substrate via-hole by a dry etching using chlorine gas of related art, when etching from the backside side, not only the semiconductor substrate such as GaAs and Si for the via-hole on the backside, wiring materials such as Au, Cu, Al, Ti, Ta, W, Mo, TiN and WSi buried in the via-hole on the surface side is also etched. There is a problem that if the via line buried in the via-hole on the surface side is etched in this way, there is a problem of causing a disconnection of the lines.